High Performance Converged Ethernet Interface Engine
Chelsio’s Terminator Core IP is a configurable, high performance Ethernet packet processing engine with a full suite of software, suitable for a wide range of SoC network connectivity solutions. At the heart of the Terminator line of silicon proven Network Interface Card (NIC) controllers, Chelsio’s Core architecture is designed for low latency, high capacity cut-through processing, minimum cycles per byte (CPB) and maximum memory efficiency.
Terminator Core is the culmination of more than a decade of expertise with high performance network protocol implementation, and five generations of field proven designs. It offers support for a complete suite of storage and high performance computing networking protocols. Integrating the Core in an SoC design provides a drop-in server grade Ethernet managed and hyper-virtualized network controller. An optional edge switch component provides flexible packet replication and switching, with access control support.
The Terminator Core architecture is highly integrated with a single ACE or PCI interface on the system bus side, and one or more 25/40Gbps low latency connections to Ethernet ports on the network side. The Core connects to an ARM or other embedded CPU based SoC system, and can be configured to support a comprehensive set of offload networking, storage and compute protocols, including a complete list of stateless offloads:
- Large Send Offload (LSO) and Large Receive Offload (LRO)
- Checksum offloads for TCP/UDP over IPv4/IPv6
- CRC offloads for RDMA, FCoE and iSCSI
- Load balancing – RSS
- Drop/Steer/Route filters and NAT offload
- NVGRE/VXLAN/GENEVE offload
- Timestamping, sniffing, tracing and other NFV features
The Core can also be configured to support one or more of the stateful offloads:
- iSCSI – PDU and full offload with T10-DIX
- FCoE – PDU and full offload with T10-DIX
- iWARP RDMA over Ethernet
- TCP/IP and UDP/IP sockets
The ACE version also supports an optional ccNUMA controller which allows native integration within the SoC memory subsystem.